1. Field of the Invention
The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a top package of a PoP (package-on-package) for memory die.
2. Description of Related Art
Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages.
One limitation in reducing the size of a package (e.g., either the top package (the memory package) or the bottom package (the SoC package) in the PoP package) is the size of the substrate used in the package. Thin substrates and/or coreless substrates (e.g., laminate substrates) have been used to reduce the size of the packages to certain levels. Further reductions in size, however, may be needed in order to provide even smaller packages for next generation devices.
One or more memory die are typically placed in the top package of a PoP package. Using a single memory die (e.g., a single 8 GB (gigabyte) DDR (double date rate) memory die) in the top package is achieved relatively easy (e.g., connections to terminals on the package are reliable and simple to make and the top package has a relatively thin profile). The single memory die, however, may not provide sufficient capability for newer and more powerful devices. Thus, devices requiring larger memory capability typically need two or more die in the top package (e.g., two or more 8 GB DDR memory die).
A typical configuration for putting two memory die in a top package is to vertically stack the memory die (e.g., stack one memory die directly on top of another memory die). Vertically stacking the memory die reduces the overall thickness of the top package. Stacking the die vertically, however, creates problems with connecting both die to terminals on the package. Typically, the die are connected to the terminals using wire bonding between the top of the memory die (with at least part of the bottom memory die in the stack protruding beyond the edge of the top memory die) and terminals on the substrate of the top package. Using wire bonding, however, increases the height of the top package as the wire bond paths are spaced to prevent shorting of the different wire bonds from each memory die. In addition, wire bonding may provide a high impedance path that reduces signal integrity and/or power integrity between the memory die and the terminals. A possible solution to overcome the problems with wire bonding is to provide through silicon vias (TSVs) from the memory die to the terminals in the top package. Providing TSVs, however, requires special memory die, adds several additional process steps, and is relatively expensive.